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0x0E - IRQCFG0E [default 0x01]
Name
Bits
R/W
Description
FIFO fill mode selection:
Start_Fill
7
r/w
0 → FIFO starts filling when start pattern is detected
1 → FIFO fills as long as Start_Det is 1
Start of FIFO fill:
Start_Fill = 0, goes high when start pattern detected. Write a 1 to reset this bit and
Start_Det
6
r/w/c
start pattern detect.
Start_Fill = 1
0 → Stop filling FIFO
1 → Start filling FIFO
Transmit state:
TX_STOP
5
r
0 → Transferring bits to the TX modulator
1 → Last bit transferred to the TX modulator
Buffered data mode:
0 → Start transmit when FIFO is full (IRQ0 mapped to nFIFOEMPY)
1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY)
Start_Full
4
r/w
Packet data mode:
0 → Start transmit when bytes equal or greater than FIFO_thresh value (IRQ0 mapped to
FIFO_thresh for FIFO_Int_Tx)
1 → Start transmit when nFIFOEMPY = 1 (IRQ0 mapped to nFIFOEMPY)
Enables SIG_DETECT:
RSSI_Int
3
r/w
0 → Disable interrupt
1 → Enable interrupt
Detects a signal above the RSSI_thld:
SIG_DETECT
2
r/w/c
0 → Signal lower than threshold
1 → Signal equal or greater than the RSSI_thld level
This bit must be cleared by writing a 1 to its location.
Detects the PLL lock status:
PLL_LOCK_ST
1
r/w/c
0 → PLL not locked
1 → PLL locked
This bit latches high each time the PLL locks and must be cleared by writing a 1 to its location.
Enables the PLL_LOCK signal on Pin 23
PLL_LOCK_EN
0
r/w
0 → PLL_LOCK signal disabled, Pin 23 set high
1 → PLL_LOCK signal enabled
Table 27
0x0F - IRQCFG0F [default 0x00]
Name
RSSI_thld
Bits
7..0
R/W
r/w
Description
RSSI threshold level for interrupt.
RSSI_thld default is 0x00
Table 28
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Page 33 of 65
TRC103 - 11/29/12
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